Bala Chavali

AMD

Bala Chavali earned her Bachelor's of Science degree in Electrical and Computer Engineering from the University of Houston. She began her electrical career at Texas Instruments as an Application Engineer and advanced her career as SoC Architect and SoC Systems lead. After 8 years at Texas Instruments, she moved to Altera/Intel as an SoC Debug Architect and worked on FPGA and Security Architecture also. She held roles including System Engineer, System Integrator, and Design Engineer, all of which provided the background leading to her expertise in functional safety at both Intel and Texas Instruments. Currently she is a Principal Member of Technical Staff at AMD and is chartered with driving technical innovation across RAS (Reliability Availability and Serviceability) and Functional Safety. 

She has over 15 years of industry experience focusing on safety critical systems in automotive and industrial markets with expertise in SoCs and FPGAs. She has multiple patent awards in embedded systems and functional safety. She is an active member of multiple industry working groups such as Accellera, IEEE P2851, and IEEE P2846. She is currently Vice Chair of the Accellera FUSA working group.